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fin224ac 22bit bidirectional serializer/deseri alizer april 2011 ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.6 click here for this datasheet translated into korean! fin224ac 22bit bidirectional serializer/deserializer features ? industry smallest 22bit serializer/deserializer p air ? low power for minimum impact on battery life C multiple powerdown modes ? 100na in standby mode, 5ma typical operating conditions ? highly rolled lvcmos edge rate option to meet regulatory requirements ? cable reduction: 25:4 or greater ? differential signaling: CC90dbm emi when using ctl in lab conditions Cminimized shielding Cminimized emi filter Cminimum susceptibility to external interference ? up to 22 bits in either direction ? voltage translation from 1.65v to 3.6v ? high esd protection: > 15kv hbm ? parallel i/o power supply (v ddp ) range, 1.65v 3.6v ? can support microcontroller or rgb pixel interface applications ? image sensors ? small displays C lcd, cell phone, digital camera, portable gaming, printer, pda, video camera, automotive description the fin224ac serdes? is a lowpower serializer/ deserializer (serdes) that can help minimize the co st and power of transferring wide signal paths. throug h the use of serialization, the number of signals transfe rred from one point to another can be significantly redu ced. typical reduction is 4:1 to 6:1 for unidirectional paths. for bidirectional operation, using half duplex for multiple sources, it is possible to reach signal reduction c lose to 10:1. through the use of differential signaling, sh ielding and emi filters can also be minimized, further redu cing the cost of serialization. the differential signali ng is also important for providing a noiseinsensitive signal that can withstand radio and electrical noise sources. major reduction in power consumption allows minimal impac t on battery life in ultraportable applications. it is possible to use a single pll for most applications including bi directional operation. fin224ac to fin24ac comparison ? up to 20% power reduction ? double wide ckp pulse on fin224ac, mode 3 ? rolled edge rate for deserializer outputs on fin224ac, for single display applications ? same voltage range ? same pinout and package ordering information serdes tm is a trademark of fairchild semiconductor corporat ion. order number operating temperature range package description packing method fin224acgfx 30 to +70c 42ball, ultrasmall scale ball grid array (ussbga ), jedec mo195, 3.5mm wide (slow lvcmos edge rate) tape and reel fin224acmlx 30 to +70c 40terminal, molded leadless package (mlp), quad, jedec mo220, 6mm square (slow lvcmos edge rate) tape and reel
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.6 2 fin224ac 22bit bidirectional serializer/deseria lizer basic concept figure 1. conceptual diagram functional block diagram figure 2. block diagram fin224ac serializer fin224ac deserializer ctl 4 lvcmos 22 lvcmos 22 ckref cks0+ cksi+ +- +- +- +- cksi- cksint cksint oe oe dso+/dsi- serializer control word ck generator freq control direction control power down control control logic 0 i serializer deserializerdeserializer control pll register register register dso-/dsi+ diro cks0- ckp s1s2 diri strobe dp[21:22] dp[23:24] dp[1:20] 100 te r mination 100 gated te r mination
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.6 3 fin224ac 22bit bidirectional serializer/deseria lizer terminal description note : 1. the dso/dsi serial port pins have been arranged such that if one device is rotated 180 degrees with respect to the other device, the serial connections properly align without the need for any traces or cable signals t o cross. other layout orientation may require that traces or cable s cross. terminal name i/o type number of terminals description of signals dp[1:20] i/o 20 lvcmos parallel i/o, direction cont rolled by diri pin dp[21:22] i 2 lvcmos parallel unidirectional inputs dp[23:24] o 2 lvcmos unidirectional parallel output s ckref in 1 lvcmos clock input and pll reference strobe in 1 lvcmos strobe signal for latching data into the serializer ckp out 1 lvcmos word clock output dso+ / dsi dso / dsi+ diffi/o 2 ctl differential serial i/o data signals (1.) dso: refers to output signal pair dsi: refers to input signal pair dso(i)+: positive signal of dso(i) pair dso(i): negative signal of dso(i) pair cksi+ cksi diffin 2 ctl differential deserializer input bit clock cksi: refers to signal pair cksi+: positive signal of cksi pair cksi: negative signal of cksi pair ckso+ ckso diffout 2 ctl differential serializer output bit clock ckso: refers to signal pair ckso+: positive signal of ckso pair ckso: negative signal of ckso pair s1 in 1 lvcmos mode selection terminals used to select freq uency range for the reflect, ckref s2 in 1 diri in 1 lvcmos control input used to control direction of d ata flow: diri = 1 serializer diri = 0 deserializer diro out 1 lvcmos control output inversion of diri v ddp supply 1 power supply for parallel i/o and translat ion circuitry v dds supply 1 power supply for core and serial i/o v dda supply 1 power supply for analog pll circuitry gnd supply 2 for ground signals (2 for bga, 1 for mlp)
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.6 4 fin224ac 22bit bidirectional serializer/deseria lizer connection diagrams figure 3. terminal assignments for mlp (top view) figure 4. terminal assignments for bga (top view) 12 3 4 5 6 7 8 9 10 dp[9] dp[10] dp[11] dp[12] v ddp ckp dp[13]dp[14] dp[15] dp[16] 3029 28 27 26 25 24 23 22 21 dirockso+ ckso- dso+ dso- cksi- cksi+ diri s2 v dds 1112 13 14 15 16 17 18 19 20 dp[17]dp[18] dp[19] dp[20] dp[21] dp[22] dp[23] dp[24] s1 v dda 4039 38 37 36 35 34 33 32 31 dp[8]dp[7] dp[6] dp[5] dp[4] dp[3] dp[2] dp[1] strobe ckref 42 mbga pa ckage 3.5mm x 4.5mm (.5mm pitcth) (top vie w) 1 2 3 4 5 6 a b c d e f g pin assignments 1 2 3 4 5 6 a dp[9] dp[7] dp[5] dp[3] dp[1] ckref b dp[11] dp[10] dp[6] dp[2] strobe diro c ckp dp[12] dp[8] dp[4] ckso+ ckso d dp[13] dp[14] vddp gnd dso/dsi+ dso+/dsi e dp[15] dp[16] gnd vdds cksi+ cksi f dp[17] dp[18] dp[21] vdda s2 diri g dp[19] dp[20] dp[22] dp[23] dp[24] s1
fin224ac 22bit bidirectional serializer/deseria lizer ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.6 5 control logic circuitry the fin224ac has the ability to be used as a 22bit seri alizer or a 22bit deserializer. pins s1 and s2 mus t be set to accommodate the clock reference input freque ncy range of the serializer. table 1 shows the pin prog ram ming of these options based on the s1 and s2 contro l pins. the diri pin controls whether the device is a serial izer or a deserializer. when diri is asserted low, the device is configured as a deserializer. when the di ri pin is asserted high, the device is configured as a ser ial izer. changing the state on the diri signal revers es the direction of the i/o signals and generate the oppos ite state signal on diro . for unidirectional operation the diri pin should be hardwired to the high or low sta te and the diro pin should be left floating. for bidirec tional operation, the diri of the master device is driven by the system and the diro signal of the master is used to drive the diri of the slave device. serializer/deserializer with dedicated i/o variatio n the serialization and deserialization circuitry is set up for 24 bits. because of the dedicated inputs and output s, only 22 bits of data are serialized or deserialized . dp[21:22] inputs to the serializer are transmitted to dp[23:24] outputs on the deserializer. turnaround functionality the device passes and inverts the diri signal throu gh the device asynchronously to the diro signal. care must be taken by the system designer to ensure that no contention occurs between the deserializer outputs and the other devices on this port. optimally the perip heral device driving the serializer should be put into a high impedance state prior to the diri signal being asse rted. when a device with dedicated data outputs turns fro m a deserializer to a serializer, the dedicated outputs remain at the last logical value asserted. this value only changes if the device is once again turned around i nto a deserializer and the values are overwritten. powerdown mode: (mode 0) mode 0 is used for powering down and resetting the device. when both of the mode signals are driven to a low state, the pll and references are disabled, dif fer ential input buffers are shut off, differential out put buffers are placed into a highimpedance state, lvcmos out puts are placed into a highimpedance state, and lv c mos inputs are driven to a valid level internally. additionally all internal circuitry is reset. the l oss of ckref state is also enabled to ensure that the pll only powersup if there is a valid ckref signal. in a typical application mode, signals of the devic e do not change states other than between the desired freque ncy range and the powerdown mode. this allows for sys temlevel powerdown functionality to be implemente d via a single wire for a serdes pair. the s1 and s2 selec tion signals that have their operating mode driven to a logic 0 should be hardwired to gnd. the s1 and s2 signals that have their operating mode driven to a logic 1 should be connected to a systemlevel powerdown or reset signal. table 1. control logic circuitry mode number s2 s1 diri description 0 0 0 x powerdown mode 1 0 1 1 22bit serializer 2mhz to 5mhz ckref 0 1 0 22bit deserializer 2 1 0 1 22bit serializer 5mhz to 15mhz ckref 1 0 0 22bit deserializer 3 1 1 1 22bit serializer 10mhz to 26mhz ckref (divid e by 2 serial data) 1 1 0 22bit deserializer
fin224ac 22bit bidirectional serializer/deseria lizer ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.6 6 serializer operation mode the serializer configurations are described in the follow ing sections. the basic serialization circuitry wor ks essentially identically in these modes, but the act ual data and clock streams differ depending on if ckref is t he same as the strobe signal or not. when it is stated that ckref does not equal strobe, each signal is di s tinct and ckref must be running at a frequency high enough to avoid any loss of data condition. ckref m ust never be a lower frequency than strobe. serializer operation: mode 1 or mode 2, diri = 1, ckref = strobe the pll must receive a stable ckref signal to achie ve lock prior to any valid data being sent. the ckref sig nal can be used as the data strobe signal provided that data can be ignored during the pll lock phase. once the pll is stable and locked, the device can b egin to capture and serialize data. data is captured on the ris ing edge of the strobe signal and serialized. when operating in serializer mode, the internal deserial izer cir cuitry is disabled; including the serial clock, ser ial data input buffers, bidirectional parallel outputs, and ckp word clock. the ckp word clock is driven high. serializer operation: diri = 1, ckref does not = strobe if the same signal is not used for ckref and strobe , the ckref signal must be run at a higher frequency than the strobe rate to serialize the data correctl y. the actual serial transfer rate remains at 13 times the ckref frequency. a data bit value of zero is sent w hen no valid data is present in the serial bit stream. the oper ation of the serializer otherwise remains the same. the exact frequency that the reference clock needs to run at depends upon the stability of the ckref and strobe signal. if the source of the ckref signal implements spread spectrum technology, the minimun frequency of the spread spectrum clock should be us ed in calculating the ratio of strobe frequency to the ckref frequency. similarly, if the strobe signal ha s significant cycletocycle variation, the maximum c ycle tocycle time needs to be factored into the selecti on of the ckref frequency. serializer operation: mode 3 (s1 = s2 =1), diri =1. ckref divide by 2 mode. when operating in mode 3, the effective serial spee d is divided by two. this mode has been implemented to accommodate cases where the reference clock fre quency is high compared to the actual strobe freque ncy. the actual strobe frequency must be less than or eq ual to 50% of the ckref frequency for this mode to work properly. this mode, in all other ways, operates th e same as described in the section where ckref does not equal strobe. serializer operation: diri = 1, no ckref a third method of serialization can be acheived by pro viding a freerunning bit clock on the cksi signal. this mode is enabled by grounding the ckref signal and driving the diri signal high. at powerup, the devi ce is configured to accept a serialization clock from cks i. if a ckref is received, this device enables the ckref se ri alization mode. the device remains in this mode eve n if ckref is stopped. to reenable this mode, the devic e must be powered down and then powered back up with a logic 0 on ckref. deserializer operation mode the operation of the deserializer is dependent on t he data received on the dsi data signal pair and the c ksi clock signal pair. the following sections describe the operation of the deserializer under distinct serial izer source conditions. references to the ckref and strobe signals refer to the signals associated with the serializer device generating the serial data and cl ock sig nals that are inputs to the deserializer. when oper ating in deserializer mode, the internal serializer circuitr y is dis abled, including the parallel data input buffers. i f there is a ckref signal provided, the ckso serial clock cont in ues to transmit bit clocks. upon powerup (s1 or s2 = 1), deserializer output data pins are driven low until valid data is passed through the deserializer. deserializer operation: diri = 0 (serializer source: ckref = strobe) when the diri signal is asserted low, the device is configured as a deserializer. data is captured on t he serial port and deserialized through use of the bit clock sent with the data. deserializer operation: diri = 0 (serializer source: ckref does not = strobe) the logical operation of the deserializer remains t he same if the ckref is equal in frequency to the stro be or at a higher frequency than the strobe. the actua l serial data stream presented to the deserializer is differ ent because it has nonvalid data bits sent between words. the duty cycle of ckp varies based on the ra tio of the frequency of the ckref signal to the strobe signal. the frequency of the ckp signal is equal to the strobe frequency. in modes 1 and 2, the ckp low time equals half of the ckref period of the seriali zer. in mode 3, the ckp low is equal to the ckref period. the ckp high time is approximately equal to the strobe period, minus the ckp low time.
fin224ac 22bit bidirectional serializer/deseria lizer ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.6 7 lvcmos data i/o the lvcmos input buffers have a nominal threshold value equal to half v dd . the input buffers are only oper ational when the device is operating as a serialize r. when the device is operating as a deserializer, the inputs are gated off to conserve power. the lvcmos 3state output buffers are rated for a source / sink current of approximately 0.5ma at 1.8 v. the outputs are active when the diri signal and eit her s1 or s2 is asserted high. when the diri signal and either s1 or s2 is asserted low, the bidirectiona l lvc mos i/os is in a highz state. under purely capacit ive load conditions, the output swings between gnd and v ddp . when s1 or s2 initially transitions high, the ini tial state of the deserializer lvcmos outputs is zero. unused lvcmos input buffers must be either tied off to a valid logic low or a valid logic high level to pr event static current draw due to a floating input. unused lvc mos output should be left floating. unused bidirec tional pins should be connected to gnd through a highvalu e resistor. if a fin224ac device is configured as an unidi rectional serializer, unused data i/o can be treate d as unused inputs. if the fin224ac is hardwired as a de seri alizer, unused data i/o can be treated as unused outputs.
fin224ac 22bit bidirectional serializer/deseria lizer ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.6 8 application mode diagrams figure 5. fin224ac rgb figure 6. fin224ac microcontroller flex circuit design guidelines the serial i/o information is transmitted at a high serial rate. care must be taken implementing this serial i/o flex cable. the following best practices should be used when developing the flex cabling or flex pcb: keep all four differential wires the same length. allow no noisy signals over or near differential se rial wires. example: no lvcmos traces over differen tial wires. use only one ground plane or wire over the differen tial serial wires. do not run ground over top and b ottom. do not place test points on differential serial wir es. use differential serial wires a minimum of 2cm away from the antenna. 2.8v 2.8v vddp 2.8v 1.8v lcd _vs ync _s lcd 14_m lcd 10_m lcd 2_m lcd 6_m lcd 8_m lcd 12_m lcd 4_m lcd 1_m lcd 15_m lcd 5_m lcd 11_m lcd 3_m lcd 9_m lcd 7_m lcd 13_m pix clk _m lcd _hs ync _m lcd _vs ync _m lcd 17_m lcd 0_s lcd 1_s lcd 0_m lcd 2_s lcd 3_s lcd 4_s lcd 5_s pix clk _s gpi o_mode lcd 6_s lcd 7_s lcd 8_s lcd 9_s lcd 10_s lcd 11_s lcd 12_s lcd 13_s lcd 14_s lcd 15_s lcd _hs ync _s lcd 16_s lcd 17_s lcd 16_m lcd _en abl e_ m lcd _en abl e_ s ser des deserializer lcd con tro ller out assu mpt ion s: 1) 18 -b it uni dir ect ion al rgb ap pli cat ion 2) mod e 3 op era tio n ( 10 m hz to 20mh z c kre f) lcd dis play in 3) vddp = ( 1.65v t o 3. 6v) se r des se ria liz er c11 2.2u f c11 2.2 f 1nf c10 1nf c10 tp5 tp5 .01 uf c3 .01 f c3 1nf c6 1nf c6 u22 fin 224ac u22 fin 224ac dp9 a1 dp7 a2 dp5 a3 dp3 a4 dp1 a5 ckr ef a6 dp1 1 b1 dp1 0 b2 dp6 b3 dp2 b4 str obe b5 dir o b6 ckp c1 dp1 2 c2 dp8 c3 dp4 c4 cks o+ c5 cks o- c6 dp1 3 d1 dp1 4 d2 vddp d3 gn d d4 dso -/d si + d5 dso +/d si - d6 cks i- e6 cks i+ e5 vdds e4 gn d e3 dp1 6 e2 dp1 5 e1 dir i f6 s2 f5 vdda f4 dp2 1 f3 dp1 8 f2 dp1 7 f1 s1 j6 dp2 4 j5 dp2 3 j4 dp2 2 j3 dp2 0 j2 dp1 9 j1 tp6 tp6 u20 fin 224ac u20 fin 224ac dp9 a1 dp7 a2 dp5 a3 dp3 a4 dp1 a5 ckr ef a6 dp1 1 b1 dp1 0 b2 dp6 b3 dp2 b4 str obe b5 dir o b6 ckp c1 dp1 2 c2 dp8 c3 dp4 c4 cks o+ c5 cks o- c6 dp1 3 d1 dp1 4 d2 vddp d3 gn d d4 dso -/d si + d5 dso +/d si - d6 cks i- e6 cks i+ e5 vdds e4 gn d e3 dp1 6 e2 dp1 5 e1 dir i f6 s2 f5 vdda f4 dp2 1 f3 dp1 8 f2 dp1 7 f1 s1 j6 dp2 4 j5 dp2 3 j4 dp2 2 j3 dp2 0 j2 dp1 9 j1 .01 uf c12 .01 f c12 2.8v 1.8v vddp 2.8v 2.8v lcd14_mlcd10_m lcd2_m lcd6_m lcd8_m lcd12_m lcd4_mlcd1_m lcd15_m lcd5_m lcd11_m lcd9_mlcd7_m lcd13_m refclk lcd3_m gpio_mode lcd_/write_enable_m lcd16_m lcd17_m lcd0_s lcd0_m lcd_address_m lcd_/cs_m lcd1_s lcd2_s lcd3_s lcd4_s lcd5_s lcd6_s lcd7_s lcd8_s lcd9_s lcd10_s lcd11_s lcd12_s lcd13_s lcd14_s lcd15_s lcd16_s lcd17_s lcd_address_s lcd_/cs_s lcd_/write_enable_s serdes serializer lcd controller out lcd display in assumptions: 1) 18-bit unidirectional controller application 2) mode 3 operation (10 mhz to 20mhz ckref) ser des deserializer 3) vddp= (1.65v to 3.6v)4) refclk is a continously running clock with a frequency greater than /write_enable. u23 fin224ac u23 fin224ac dp9 a1 dp7 a2 dp5 a3 dp3 a4 dp1 a5 ckref a6 dp11 b1 dp10 b2 dp6 b3 dp2 b4 strobe b5 diro b6 ckp c1 dp12 c2 dp8 c3 dp4 c4 ckso+ c5 ckso- c6 dp13 d1 dp14 d2 vddp d3 gn d d4 dso-/dsi+ d5 dso+/dsi- d6 cksi- e6 cksi+ e5 vdds e4 gn d e3 dp16 e2 dp15 e1 diri f6 s2 f5 vdda f4 dp21 f3 dp18 f2 dp17 f1 s1 j6 dp24 j5 dp23 j4 dp22 j3 dp20 j2 dp19 j1 tp2 tp2 1nf c71nf c7 1nf c5 1nf c5 .01uf c9 .01f c9 tp1 tp1 u21 fin224ac u21 fin224ac dp9 a1 dp7 a2 dp5 a3 dp3 a4 dp1 a5 ckref a6 dp11 b1 dp10 b2 dp6 b3 dp2 b4 strobe b5 diro b6 ckp c1 dp12 c2 dp8 c3 dp4 c4 ckso+ c5 ckso- c6 dp13 d1 dp14 d2 vddp d3 gn d d4 dso-/dsi+ d5 dso+/dsi- d6 cksi- e6 cksi+ e5 vdds e4 gn d e3 dp16 e2 dp15 e1 diri f6 s2 f5 vdda f4 dp21 f3 dp18 f2 dp17 f1 s1 j6 dp24 j5 dp23 j4 dp22 j3 dp20 j2 dp19 j1 tp3 tp3 .01uf c2 .01f c2 c82.2uf c8 2.2f
fin224ac 22bit bidirectional serializer/deseria lizer ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.6 9 absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be opera ble above the recommended operating conditions and stressing the parts to these levels is not recommen ded. in addi tion, extended exposure to stresses above the recom mended operating conditions may affect device relia bility. the absolute maximum ratings are stress ratings only. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recomme nded operating conditions are specified to ensure optima l performance to the datasheet specifications. fair child does not recommend exceeding them or designing to absolute m aximum ratings. note : 2. absolute maximum ratings are dc values beyond wh ich the device may be damaged or have its useful li fe impaired. the datasheet specification should be met, without exception, to ensure that the system design is reli able over its power supply, temperature, and output/input loading variables. fairchild does not recommend operation outside datasheet specifications. symbol parameter min. max. unit v dd supply voltage 0.5 +4.6 v all input/output voltage 0.5 +4.6 v i os ctl output shortcircuit duration continuous t stg storage temperature range 65 +150 c t j maximum junctiontemperature +150 c t l lead temperature (soldering 4 seconds) +260 c esd iec6100042 15.0 kv human body model, jesd22a114, serial i/o pin 8.0 human body model, jesd22a114, all pins 2.5 charged device model, jesd22c101 2.0 symbol parameter min. max. unit v dda , v dds supply voltage 2.5 3.3 v v ddp supply voltage 1.65 3.60 v t a operating temperature (2.) 30 +70 c v ddapp supply noise voltage 100 mv pp
fin224ac 22bit bidirectional serializer/deseria lizer ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.6 10 dc electrical characteristics values are for oversupply voltage and operating te mperature ranges, unless otherwise specified. typical values are given for v dd = 2.775v and t a = 25c. positive current values refer to the curre nt flowing into the device and negative values refer to the current flowing out of the pins . voltages are referenced to ground unless otherwis e specified (except ? v od and v od ). symbol parameter test conditions min. typ. max. unit lvcmos i/o v ih input high voltage 0.65 x v ddp v ddp v il input low voltage gnd 0.35 x v ddp v v oh output high voltage i oh = 2.0ma v ddp = 3.30.30 0.75 x v ddp v v ddp = 2.50.20 v ddp = 1.80.18 v ol output low voltage i ol = 2.0ma v ddp = 3.30.30 0.25 x v ddp v v ddp = 2.50.20 v ddp = 1.80.18 i in input current v in = 0v to 3.6v 5.0 5.0 a differential i/o i odh output high source current v os = 1.0v 1.75 ma i odl output low sink current v os = 1.0v 0.950 ma i os shortcircuit output current v out = 0v driver enabled ma driver disabled 5 a i oz disabled output leakage current ckso, dso = 0v to v dds s2 = s1 = 0v 1 5 a i th differential input threshold high current 50 a i tl differential input threshold low current 50 a i iz disabled input leakage current cksi, dsi = 0v to v dds s2 = s1 = 0v 1 5 a i is shortcircuit input current v out = v dds ma v icm input common mode range v dds = 2.775 5% 0.5 v dds1 v r trm cksi, ds internal receiver termination resistor v id = 50mv, v ic = 925mv, diri = 0 | cksi + C cksi C | = v id 100
fin224ac 22bit bidirectional serializer/deseria lizer ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.6 11 power supply currents typical values are given for v dd = 2.775v and t a = 25c. positive current values refer to the curre nt flowing into the device and negative values refer to the current flo wing out of the pins. voltages are referenced to gr ound unless otherwise specified (except ? v od and v od ). symbol parameter test conditions min. typ. max. unit idda1 vdda serializer static supply current all dp and control inputs at 0v or nockref, s2 = 0, s1 = 1, dir = 1 450 a idda2 vdda deserializer static supply current all dp and control inputs at 0v or nockref, s2 = 0, s1 = 1, dir = 0 550 a idds1 vdds serializer static supply current all dp and control inputs at 0v or nockref, s2 = 0, s1 = 1, dir = 1 4 ma idds2 vdds deserializer static supply current all dp and control inputs at 0v or nockref, s2 = 0, s1 = 1, dir = 0 4.5 ma idd_pd vdd powerdown supply current idd_pd = idda s1 = s2 = 0 all inputs at gnd or vdd 0.1 a idd_ser1 26:1 dynamic serializer power supply current idd_ser1 = idda+idds+iddp ckref = strobe diri = h s2 = 0 s1 = 1 1.2mhz 9 ma 5mhz 14 s2 = 1 s1 = 0 5mhz 9 15mhz 17 s2 = 1 s1 = 1 10mhz 9 26mhz 16 idd_des1 26:1 dynamic deserializer power supply current idd_des1 = idda+idds+iddp ckref = strobe diri = l s2 = 0 s1 = 1 2mhz 5 ma 5mhz 6 s2 = 1 s1 = 0 5mhz 4 15mhz 5 s2 = 1 s1 = 1 10mhz 7 26mhz 11 idd_ser2 26:1 dynamic serializer power supply current idd_ses2 = idda+idds+iddp no ckref strobe active cksi = 15x strobe diri = h 2mhz 8 ma 5mhz 8 10mhz 10 15mhz 12
fin224ac 22bit bidirectional serializer/deseria lizer ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.6 12 ac electrical characteristics characteristics at recommended oversupply voltage and operating temperature ranges, unless otherwise specified. typical values are given for v dd = 2.775v and t a = 25c. positive current values refer to the curre nt flowing into device and negative values means current flowing ou t of the pins. voltages are referenced to ground un less other wise specified (except ? v od and v od ). symbol parameter test conditions min. typ. max. uni t serializer input operating conditions t tcp ckref clock period (2mhz C 26mhz) ckref = strobe figure 7. s2=0 s1=1 200 500 ns s2=1 s1=0 66 200 s2=1 s1=1 38.46 100.00 f ref ckref frequency relative to strobe ckref does not = strobe s2=0 s1=1 2.25 x f strobe mhz t cpwh ckref clock high time 0.2 0.5 t t cpwl ckref clock low time 0.2 0.5 t t clkt lvcmos input transition time figure 9. 90.0 ns t spwh strobe pulse width high/low figure 9. (tx4)/26 (tx22 )/26 ns f max maximum serial data rate ckref x 26 s2=0 s1=1 52 130 mb/s s2=1 s1=0 130 390 s2=1 s1=1 260 676 t stc dp (n) setup to strobe diri = 1 2.5 ns t htc dp (n) hold to strobe 2.0 ns serializer ac electrical characteristics t tccd transmitter clock input to clock output delay ckref = strobe 33a+1.5 35a+6.5 ns t spos ckso position relative to ds (3.) 50 250 ps pll ac electrical characteristics t tplls0 serializer phase lock loop stabilization time figure 11. 200 s t tplld0 pll disable time loss of clock figure 12. 30 s t tplld1 pll powerdown time (4.) figure 13. 20 ns deserializer input operating conditions t s_ds serial port setup time, dstocksi (5.) 1.4 ns t h_ds serial port hold time, dstocks (5.) 250 ps deserializer ac electrical characteristics t rcop deserializer clock output (ckp out) period (6.) figure 10. 50 500 ns t rcol ckp out low time (6.) (rising edge strobe) serializer source strobe = ckref figure 10. 13a3 13a+3 ns t rcoh ckp out high time 13a3 13a+3 ns t pdv data valid to ckp low (rising edge strobe) figure 10. 8a6 8a+1 ns t rolh output rise time (20% to 80%) c l = 8pf figure 7. 18 ns t rohl output fall time (20% to 80%) c l = 8pf figure 7. 18 ns
fin224ac 22bit bidirectional serializer/deseria lizer ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.6 13 notes : 3. skew is measured from either the rising or fallin g edge of ckso clock to the rising or falling edge of data (dso). signals are edge aligned. both outputs should have identical load conditions for this test to be valid . 4. the powerdown time is a function of the ckref fr equency prior to ckref being stopped high or low an d the state of the s1/s2 mode pins. the specific number o f clock cycles required for the pll to be disabled varies dependent upon the operating mode of the device. 5. signals are transmitted from the serializer sourc e synchronously. note that, in some cases, data is transmitted when the clock remains at a high state. skew should only be measured when data and clock are transitioning at the same time. total measured input skew would be a combinat ion of output skew from the serializer, load variat ions, and isi and jitter effects. 6. a = (1/f)/13) rising edge of ckp appears approximately 13 bit tim es after the falling edge of the ckp output. fallin g edge of ckp occurs approximately eight bit times af ter a data transition or six bit times after the fa lling edge of ckso. variation of the data with respect to the ckp signal is due to internal propagation delay differ ences of the data and ckp path and propagation delay differences on the various data pins. note that if the ckref i s not equal to strobe for the serializer, the ckp signal does n ot maintain a 50% duty cycle.the low time of ckp re mains 13 bit times. control logic timing controls note : 7. deserializer enable time includes the time requir ed for internal voltage and current references to s tabilize. this time is significantly less than the pll lock time and th erefore does not limit overall system startup time. capacitance symbol parameter test conditions min. typ. max. uni ts t phl_dir , t plh_dir propagation delay diritodiro diri lowtohigh or hightolow 17 ns t plz , t phz propagation delay diritodp diri lowtohigh 25 ns t pzl , t pzh propagation delay diritodp diri hightolow 25 ns t plz , t phz deserializer disable time: s0 or s1 to dp diri = 0, s1(2) = 0 and s2(1) = lowtohigh, figure 14. 25 ns t pzl , t pzh deserializer enable time: s0 or s1 to dp diri = 0, (7.) s1(2) = 0 and s2(1) = lowtohigh figure 14. 2 s t plz , t phz serializer disable time: s0 or s1 to ckso, ds diri = 1, s1(2) = 0 and s2(1) = hightolow, figure 13. 25 ns t pzl , t pzh serializer enable time: s0 or s1 to ckso, ds diri = 1, s1(2) and s2(1) = lowtohigh, figure 13. 65 ns symbol parameter test conditions min. typ. max. unit s c in capacitance of input only signals, ckref, strobe, s1, s2, diri diri = 1, s1 = s2 = 0, v dd = 2.5v 2 pf c io capacitance of parallel port pins dp 1:12 diri = 1, s1 = s2 = 0, v dd = 2.5v 2 pf c iodiff capacitance of differential i/o signals diri = 0, s1 = s2 = 0, v dd = 2.775v 2 pf
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.6 14 fin224ac 22bit bidirectional serializer/deseria lizer ac loading and waveforms figure 7. lvcmos output load and transition times figure 8. serial setup and hold times figure 9. lvcmos clock parameters figure 10. deser ializser data valid window time and clock output parameters figure 11. serializer pll lock time t rolh 20% dpn dpn 20% 80% 80% 8pf t rohl setup: strobe dp[1:12] strobe t stc t htc data data dp[1:12] setup timehold time mo de 0 = 0 or 1, mo de 1 = 1 , ser/des = 1 ckref t clkt 90% 90% 10% 10% 50% 50% t clkt v ih v il t tcp t cpwh t cpwl ckp dp[1:12] t pdv data data time e n_des = 1 , c ksi and d s i ar e val id si gnal s ckref 50% 75% 50% 25% t rcop t rcoh t rcol setup: cks0 ckref s1 or s2 v dd / v dda t tplls0 no te: c kre f si gnal is fr ee runn in g.
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.6 15 fin224ac 22bit bidirectional serializer/deseria lizer ac loading and waveforms (continued) figure 12. pll loss of clock disable time figure 13. pll powerdown time figure 14. serializ er enable and disable time figure 15. deserializer enable and disable times cks0 ckref t tppld0 note: ck ref signal can be stopped either high or low cks0 s1 or s2 t tppld1 ds+,cks0+ highz ds+,cks0- s1 or s2 t plz(hz) t pzl(zh) note: ck ref must be active and pll must be stable s1 or s2 dp t plz(hz) t pzl(zh) note: if s1(2) transitioning the n s2(1) must = 0 for test to be valid
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.6 16 fin224ac 22bit bidirectional serializer/deseria lizer tape and reel specification mlp embossed tape dimension dimensions are in millimeters. notes : ao, bo, and ko dimensions are determined with respe ct to the eia/jedec rs481 rotational and lateral m ovement requirements (see sketches a, b, and c ). shipping reel dimension dimensions are in millimeters. package a 0 0.1 b 0 0.1 d 0.05 d 1 min. e 0.1 f 0.1 k 0 0.1 p 1 typ. p 0 typ. p 2 0/05 t typ. t c 0.005 w 0.3 w c typ. 5 x 5 5.35 5.35 1.55 1.50 1.75 5.50 1.40 8.00 4.00 2.00 0.30 0. 07 12.00 9.30 6 x 6 6.30 6.30 1.55 1.50 1.75 5.50 1.40 8.00 4.00 2.00 0.30 0. 07 12.00 9.30 tape width dia a max. dim b min. dia c +0.5/C0.2 dia d min. dim n min. dim w1 +2.0/C0 dim w2 max. dim w3 (lslCusl) 8 330.0 1.5 13.0 20.2 178.0 8.4 14.4 7.9 ~ 10.4 12 330.0 1.5 13.0 20.2 178.0 12.4 18.4 11.9 ~ 15.4 16 330.0 1.5 13.0 20.2 178.0 16.4 22.4 15.9 ~ 19.4 p 1 a 0 d 1 p 0 p 2 f w e d b 0 tc w c k 0 t user di recti on of feed 10 ma ximum c omponent ro tation sk et ch c ( t op v iew ) co mp onent l ate ra l mo ve me nt typical componentcavity center line 1.0mmmaximum w1 measured at hub dia a max dia d min b min dia c dia n see detail aa detail aa w3 w2 max measured at hub 1.0mmmaximum typical componentcenter line 10 maximum b0 a0 sketch b ( top vi ew) com ponen t r o tat i on sk et ch a ( side or fr on t s ecti ona l v i ew ) com pon en t r o tat i on
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.6 17 fin224ac 22bit bidirectional serializer/deseria lizer physical dimensions figure 16. 40terminal, molded leadless package (ml p), quad, jedec mo0220, 6mm square package drawings are provided as a service to custo mers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or dat e on the drawing and contact a fairchild semiconduc tor representative to verify or obtain the most recent revision. package specificat ions do not expand the terms of fairchilds worldwi de terms and conditions, specifically the warranty therein, which covers fai rchild products. always visit fairchild semiconductors online packa ging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ notes: a. conforms to jedec registration mo220, variatio n wjjd2 with exception that this is a sawn vers ion.. b. dimensions are in millimeters. c. dimensions and tolerances per asme y14.5m1994. d. land pattern per ipc sm782. e. width reduced to avoid solder bridging. f. dimensions are not inclusive of burrs, mold fla sh, or tie bar protrusions. g. drawing filename: mktmlp40arev3. 6.00 6.00 0.80 max 0.10 c seating plane 0.08 c 0.05 0.00 (0.20) c 0.15 c 0.15 c pin #1 ident 0.50 4.20 4.00 0.50 0.30 4.20 4.00 0.50 0.10 c a b 0.05 c 0.180.30 a b 6.38min 0.20min 4.77min 4.37max 0.28 max 0.50typ (0.80) x4 x40 e (datum a) (datum b) pin #1 id
fin224ac 22bit bidirectional serializer/deseria lizer ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.6 18 physical dimensions (continued) figure 17. 42ball, ultra small scale ball grid ar ray (ussbga), jedec mo195, 3.5mm wide note: click here for tape and reel specifications, available at: http://www.fairchildsemi.com/products/analog/packag ing/bga42.html. package drawings are provided as a service to custo mers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or dat e on the drawing and contact a fairchild semiconduc tor representative to verify or obtain the most recent revision. package specificat ions do not expand the terms of fairchilds worldwi de terms and conditions, specifically the warranty therein, which covers fai rchild products. always visit fairchild semiconductors online packa ging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ bottom view 3.50 4.50 0.5 0.5 3.0 2.5 ?0.30.05 seating plane 0.230.05 0.450.05 (0.75) (0.5) (0.35) (0.6) 0.08 c 0.10 c 0.10 c 0.890.082 1.00 max 0.210.04 (qa control value) 0.10 c c 0.15 c a b 0.05 c x42 terminal a1 corner index area 2x 2x 0.2 +0.1 0.0 land pattern recommendation
fin224ac 22bit bidirectional serializer/deseri alizer ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fin224ac rev.1.1.6 19

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